The present invention relates to transistors, and more specifically, to field effect transistors.
Switching devices based on nanostructures such as carbon nanotubes or semiconducting nanowires have enormous potential due to the high carrier mobility and small dimensions that such nanostructures can provide. However, one of the many challenges a technology based on nanostructures must overcome is compatibility with the high layout density that traditional silicon complementary metal-oxide-semiconductor (CMOS) technology currently supports. For high layout density, the nanostructures and the source/drain and gate contacts to the switching device built around each nanostructure should be precisely positioned. In silicon CMOS, this precise positioning is enabled by lithographic definition of the active area and source/drain junctions which are self-aligned to the gate.
At present, there are several different ways form nanostructures that may be used in switching devices. For example, techniques have been developed to produce nanotubes in sizeable quantities, including arc discharge, laser ablation, high pressure carbon monoxide (HiPCO), and chemical vapor deposition (CVD). Most of these processes take place in vacuum or with process gases. CVD growth of CNTs can occur in vacuum or at atmospheric pressure. Large quantities of nanotubes can be synthesized by these methods; advances in catalysis and continuous growth processes are making CNTs more commercially viable.
Each of these methods requires that the nanostructures be selected and then precisely placed. As will be understood, the placement of these tiny structures may be difficult on the scale of current CMOS technology.